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authorXANTRONIX Development2023-08-23 00:57:35 -0400
committerXANTRONIX Development2023-08-23 11:59:06 -0400
commitaee11a773bced14ae9d4ea50bc7650e020fe5650 (patch)
tree39599c46f1ec5b560132d2c09ee288376ac4b5dc /cpld
parentfca2309a418b99b701e752ad5172fad110d4d563 (diff)
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Initial commit of ZX8401 implementation
Diffstat (limited to 'cpld')
-rw-r--r--cpld/ZX8401.v40
1 files changed, 40 insertions, 0 deletions
diff --git a/cpld/ZX8401.v b/cpld/ZX8401.v
new file mode 100644
index 0000000..13f0e8b
--- /dev/null
+++ b/cpld/ZX8401.v
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+`timescale 1ns / 1ps
+
+module ZX8401 (
+ input wire drasll,
+ input wire mreqdl,
+ input wire mreq,
+ input wire [13:0] a,
+ input wire a15,
+ input wire ts1,
+ input wire ts2,
+ input wire rd,
+ input wire wr,
+ output wire [7:0] ma,
+ output wire [6:0] dma,
+ output wire casl
+);
+
+wire rd_wr = !(rd & wr);
+wire rd_wr_a15 = !(rd_wr & a15);
+wire avb = mreqdl | rd_wr_a15;
+
+assign dma[5] = (drasll & a[5]) | (!drasll & a[12]);
+assign dma[4] = (drasll & a[4]) | (!drasll & a[11]);
+assign dma[3] = (drasll & a[3]) | (!drasll & a[10]);
+assign dma[6] = (drasll & a[6]) | (!drasll & a[13]);
+assign ma[5] = (avb & a[5]) | (!avb & a[12]);
+assign ma[4] = (avb & a[4]) | (!avb & a[11]);
+assign ma[3] = (avb & a[3]) | (!avb & a[10]);
+assign ma[6] = (avb & a[6]) | (!avb & a[13]);
+assign dma[4] = (drasll & a[1]) | (!drasll & a[8]);
+assign dma[0] = (drasll & a[0]) | (!drasll & a[7]);
+assign dma[1] = (drasll & a[8]) | (!drasll & a[1]);
+assign dma[2] = (drasll & a[2]) | (!drasll & a[9]);
+assign ma[2] = (avb & a[1]) | (!avb & a[8]);
+assign ma[0] = (avb & a[0]) | (!avb & a[7]);
+assign ma[7] = (avb & ts2) | (!avb & ts1);
+assign ma[1] = (avb & a[2]) | (!avb & a[9]);
+assign casl = mreq | avb;
+
+endmodule